1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More specifically, the invention relates to a dynamic random access memory (DRAM) including a bit line contact having a self-align contact (SAC) structure, which is sandwiched between two gates, or a DRAM-embedded semiconductor memory device.
2. Description of the Related Art
Recently, a halo ion implantation process has been used for the manufacture of DRAMs or DRAM-embedded semiconductor memory devices (see, e.g., U.S. Pat. No. 6,444,548). In the halo ion implantation process, ion implantation (I/I) is performed at an angle. For example, impurities whose conductivity type is opposite to that of the source and drain are ion-implanted into the surface area of a substrate (DRAM cell), which corresponds to the edges of the gate (the end portions of the channel), through a contact hole for forming a bit line contact (CB) having an SAC structure to connect the substrate to the bit lines (formation of a diffusion preventing layer by CB halo I/I). The following problem can thus be circumvented. As a cell transistor decreases in gate length, the impurities that are ion-implanted to form the source and drain diffuse toward the edges of the gate to thereby lower the threshold voltage of the cell transistor.
However, a gate-to-gate space in which a bit-line contact is provided is gradually narrowed. Impurities are therefore becoming difficult to ion-implant exactly into the surface area of the substrate, which corresponds to the edges of the gate, even by the CB halo I/I.